Deep Dive: x86 and ARM
ARM processors handle interrupts and exceptions in a similar way to x86 processors.
Interrupts and exceptions are both triggered by external events, but they differ in how they are managed by the processor. An interrupt is an event that interrupts the normal flow of execution, while an exception is an event that is triggered by the processor itself, such as a division by zero or an invalid instruction.
When an interrupt or exception occurs, the processor stops executing the current instruction and switches to a special mode called the interrupt/exception mode. In this mode, the processor saves the current state of execution, including the current instruction pointer and processor status register, onto the stack. It then looks up the address of the interrupt or exception handler in a table called the Interrupt Vector Table (IVT) or Exception Vector Table (EVT). The processor then jumps to the address of the corresponding handler, which is typically located in the operating system's kernel.
The interrupt or exception handler then executes code to handle the event. This may involve saving additional state information onto the stack, servicing the device that generated the interrupt, or performing some other operation. When the handler is done, it returns control to the interrupted program by restoring the saved state from the stack. The interrupted program then continues executing from the point where it was interrupted.
ARM processors have two modes for handling interrupts and exceptions: the ARM mode and the Thumb mode. The ARM mode is the default mode, and is used for most operations. The Thumb mode is a more compact mode that is used for some operations when code size is a concern. When an interrupt or exception occurs, the processor switches to the appropriate mode and executes the corresponding handler.
In summary, interrupts and exceptions are an integral part of processor operation, and are used to handle external events and internal errors. ARM processors handle these events in a similar way to x86 processors, by switching to a special mode and executing a corresponding handler.
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